This invention relates to logic circuitry and in particular to memory circuitry which limits adverse effects of spurious signals.
Commonly used clocked Set-Reset Master-Slave Flip-Flop circuits set the complementary output terminals to selected logic levels in response to the set and/or reset terminals being set to a high state. Typically during a high "1" level of a clock signal used with the Flip-Flop the output signal levels of the master section can be modified in response to signals applied to the set or reset terminals. Once the set or reset input terminals reach the high level, the outputs of the master section of the Flip-Flop are set to the selected logic level and stay at selected levels even if the set or reset terminal returns to a low "0" level while the clock is still at a high "1" level. After the outputs of the master section are so modified and the clock signal goes a "1", the slave section then acts in response to signals received from the master section to set the output terminals of the Flip-Flop to the desired levels. Spurious signals at the set and reset terminals can cause the Flip-Flop to assume an incorrect state and to stay at that state even after the spurious signal has dissipated. This can introduce errors into systems used with the Flip-Flop.
It is desirable to have a Set-Reset Master-Slave Flip-Flop in which the output logic levels are not changed unless signals at the set and reset input terminals remain at a selected level from at least just before to after a transition of the clock signal which allows information to be transferred from the master section to the slave section.